Complementary metal oxide semiconductor (CMOS) image sensors are gaining in popularity over traditional charged-coupled devices (CCDs) due to certain advantages inherent in the CMOS image sensors. In particular, CMOS image sensors typically require lower voltages, consume less power, enable random access to image data, may be fabricated with compatible CMOS processes, and enable integrated single-chip cameras.
CMOS image sensors utilize light-sensitive CMOS circuitry to convert light energy into electrical energy. The light-sensitive CMOS circuitry typically comprises a photodiode formed in a silicon substrate. As the photodiode is exposed to light, an electrical charge is induced in the photodiode. The photodiode is typically coupled to a MOS switching transistor, which is used to sample the charge of the photodiode. Colors may be determined by placing filters over the light-sensitive CMOS circuitry.
The light received by pixels of the CMOS image sensor is often based on the three primary colors: red, green, and blue (R, G, B), and additional colors can be identified and/or created with various combinations and intensities (e.g., when red and green overlap they form yellow). Pixel sensitivity for receiving the incident light, however, is lowered with the trend of size reduction of pixels of the CMOS image sensor and cross-talk is caused between different pixels against incident light, especially against incident light with a long wavelength such as the red light (wavelength of about 650 nm), thereby degrading the overall performance of pixels of the CMOS image sensor.
As is known, image sensors can be designed to be illuminated from a front surface or from a back surface. Backside illumination image sensors provide an advantageous feature wherein the need to carefully place and route metallization features so as not to interfere with the optical path is eliminated, because the illumination comes from the backside of the wafer, whereas metallization is formed on the front side of the wafer. Additionally, the overall optical path, i.e., the optical distance from the focusing lens of the sensor to the actual light receiving surface of the sensor itself is typically reduced with backside illumination, relative to front-side illumination because the light need not travel through the metallization and inter-metal dielectric layers.
A disadvantage of conventional backside illumination image sensors is that some of the incident light may pass through the sensor and into the overlying dielectric layer. One way to reduce this unfavorable result would be to increase the thickness and/or reflectivity of the overlying dielectric layer. This may result, however, in defects arising during the manufacturing process. FIG. 1 illustrates two such potential defects, which may arise in a logic area 101 of an integrated circuit in which is formed an image sensor. While many details of an actual logic device are omitted from FIG. 1 for clarity, a substrate 100 is shown having shallow trench isolation features 104 formed therein. A top surface of the substrate 100 has been silicided to form a silicide layer 102. Conventionally, the silicide layer 102 will be formed using a self-aligned process, or so-called salicide process. Contact etch stop layer 106 (CESL) is formed atop the silicide layer 102 and an inter-level dielectric (ILD) 108 is formed atop the CESL 106. Contact 110 is formed by etching an opening through the ILD 108 and through the CESL 106 in order to expose, e.g., a portion of the silicide layer 102. A conductor is then formed within the opening to form contact 110. The function and manufacture of these elements is well known in the art.
In an effort to increase the reflectivity of the image sensor (which are manufactured concurrently with logic devices), the thickness of the dielectric layers (e.g., silicon oxide layer 105, ILD 108 and/or CESL 106) over, for example, a photosensitive diode 107 and transfer transistor 109 have been increased. However, such an increase in thickness also results in less process control of an etching process used to form contact openings. As a result, over-etching may occur, such as the over-etching illustrated generally at region 112. Such over-etching can have deleterious effects, such as causing unacceptable levels of leakage current, cross-talk between neighboring devices, and potentially could cause the resulting device to not perform as desired or to not perform at all.
FIG. 1 also illustrates another potential adverse consequence of over-etching in the logic region 101. As illustrated in FIG. 1, a gate stack 114 may be formed on substrate 100 and sidewall spacers 116 formed on gate stack 114, as is known. However, while the contact openings for contact 110 and contact 111 are typically done simultaneously, the etching cannot be stopped until the contact openings for contact 110 extends through the silicon oxide layer 105. This may cause the etching of the contact opening for contact 111 to overetch the sidewall spacers 116 (shown generally at region 118) and can result in undesired consequences, such as a potential short circuit of the contact 111 to the underlying substrate 100. If over-etching did not occur, sidewall spacer 116 and/or CESL 106 would have prevented the short circuit illustrated generally at 118.
Hence, what is needed is an improved image sensor device that provides for increased backside illumination quantum efficiency while avoiding the risks associated with over-etching of overlying dielectric layers.